A semiconductor memory device typically includes an array of memory cells arranged in rows and columns, with each memory cell configured to store a data bit. The memory cells within a given row of the array are coupled to a common wordline, while the memory cells within a given column of the array are coupled to a common bitline. Thus, the array includes a memory cell at each point where a wordline intersects with a bitline.
In a semiconductor memory device of the type described above, data may be written to or read from the memory cells of the array using a memory cycle that is divided into an active phase and a precharge phase, with the active phase being used to read or write one or more memory cells of the array and the precharge phase being used to precharge the bitlines to a precharge voltage in preparation for the next cycle. The precharge is an example of what is more generally referred to herein as “preset.”
Reading a given memory cell generally comprises transferring data stored within that cell to its corresponding bitline, and writing a given memory cell generally comprises transferring data into that cell from its corresponding bitline. For a given read or write operation, the corresponding memory cycle is more particularly referred to as a read cycle or a write cycle, respectively.
A write self-time tracking arrangement may be used in order to establish appropriate signal timing for write operations. For example, a conventional arrangement of this type utilizes a dummy row of memory cells and a dummy column of memory cells, also referred to as a dummy wordline and a dummy bitline, respectively, with those memory cells being configured in the same manner as the actual memory cells of the memory array. A dummy wordline driver generates a dummy wordline signal for application to the dummy wordline with the same timing as an actual wordline signal applied to an actual wordline of the memory array. The dummy wordline and dummy bitline are also known as a self-time wordline (STWL) and a self-time bitline (STBL), respectively.
The signal delay of the dummy wordline due to its resistor-capacitor (RC) time constant matches the corresponding RC signal delay of the actual wordline of the memory array. Also, the wordline loading impact of the dummy column matches the wordline loading impact of an actual bitline of the memory array. The dummy wordline signal after passing through the entire length of the dummy wordline and being subject to its RC delay discharges the dummy bitline and triggers internal data nodes of a designated memory cell of the corresponding dummy column. The transition in those internal data nodes of the designated memory cell is detected in control circuitry and utilized to reset the wordline signals, thereby providing the write self-time tracking functionality.
Write self-time tracking functionality of the type described above is particularly important for high-speed write operations, such as those involving register files and other memories typically having write cycle frequencies in the gigahertz (GHz) range. However, it can be difficult under conventional arrangements to accurately control the write signal timing, particularly over expected process, voltage and temperature (PVT) variations. For example, the use of the dummy row and column arrangement can lead to undue delay in the start of a given write operation, while also introducing significant area overhead that is often unacceptable for registers and other small memories. As a result, write memory cycle time may be increased, thereby degrading memory write performance.